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| Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Features s Description This general-purpose electronic subscriber loop interface circuit (SLIC) is optimized for low cost, while still providing a satisfactory set of features. This part is a pin-for-pin replacement for the Agere L9217 and L9218 SLICs. The L9219 requires a 5 V power supply and single battery to operate. This device offers forward and reverse battery operation. The rate of battery reversal may be ramped to meet international requirements. Additionally, a low-power scan mode, wherein all circuitry except the off-hook supervision is shut down to conserve power, is available. The dc current limit may be programmed via a single external resistor. Via the logic table, the current limit may be increased a nominal 42% above the value set by the IPROG resistor, giving the user a high-low current limit option. Device overhead is fixed and is adequate for 3.14 dBm into 900 of on-hook transmission. Both the loop supervision and ring trip supervision functions are offered with user-controlled thresholds via external resistors. The L9219 is offered with a receive gain that is optimized for interface to a first-generation type codec (L9219A). It is also offered with a gain option that is optimized for interface to a third- or fourth-generation type codec (L9219G). In both cases, minimizing external components required at this interface. Data control is via a parallel data control scheme. The device is available in a 28-pin PLCC package. It is built by using a 90 V complementary bipolar (CBIC) process. Basic forward/reverse battery SLIC functionality at a low cost Pin compatible with Agere Systems Inc. L9217 and L9218 SLICs Low active power (typical 138 mW during on-hook transmission) Low-power scan mode for low-power, on-hook power dissipation (52 mW typical) Distortion-free, on-hook transmission Convenient operating states: -- Forward active-low current limit -- Forward active-high current limit -- Reverse active-low current limit -- Reverse active-high current limit -- Low-power scan -- Disconnect (high impedance) Minimal external components required Two gain options to optimize the codec interface Adjustable supervision functions: -- Off-hook detector with hysteresis -- Ring trip detector Logic controlled high and low current limit Ramped rate of battery reversal Thermal protection with thermal shutdown indication s s s s s s s s s s s L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Table of Contents Contents Page Figures Page Features ......................................................................1 Description...................................................................1 Pin Information ............................................................4 Functional Description .................................................6 Absolute Maximum Ratings (at TA = 25 C) ................7 Recommended Operating Conditions .........................7 Electrical Characteristics .............................................8 Ring Trip Requirements ..........................................12 Test Configurations ...................................................13 Applications ...............................................................15 dc Applications........................................................19 Battery Feed.........................................................19 Current Limit.........................................................19 Overhead Voltage ............................................... 19 Rate of Battery Reversal ......................................20 Loop Range..........................................................20 Off-Hook Detection...............................................20 Ring Trip Detection ............................................. 21 Longitudinal Balance...............................................21 ac Design ................................................................22 Codec Types ........................................................22 ac Interface Network ............................................22 Receive Interface .................................................22 Example 1: Real Termination (FirstGeneration Codec) ...............................................23 Example 2: Complex Termination (FirstGeneration Codec) ...............................................25 Power Derating .......................................................27 Pin-for-Pin Compatibility with L9217/L9218 ............27 PCB Layout Information ............................................27 Outline Diagram.........................................................28 28-Pin PLCC ...........................................................28 Ordering Information..................................................29 Figure 13. Loop Current vs. Loop Voltage .............. 19 Figure 14. Off-Hook Detection Circuit ..................... 20 Figure 15. Ring Trip Equivalent Circuit and Equivalent Application .................... 21 Figure 16. ac Equivalent Circuit .............................. 23 Figure 17. Interface Circuit Using FirstGeneration Codec (5 V Battery) .......... 26 Figure 18. Interface Circuit Using FirstGeneration Codec (5 V Only Codec) ..... 26 Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Page Pin Descriptions ..................................... 4 Input State Coding .................................. 6 Supervision Coding ................................ 6 Power Supply .......................................... 8 2-Wire Port .............................................. 9 Analog Pin Characteristics .................... 10 ac Feed Characteristics ........................ 11 Logic Inputs and Outputs ...................... 12 Parts List for Loop Start Application Circuit Using T7504-Type Codec ......... 16 200 W + 680 W || 0.1 mF FirstGeneration Codec Design Parameters . 17 Parts List for Loop Start Application Circuit Using T8536-Type Codec ......... 18 FB1/FB2 Values vs. Typical Ramp Time ...................................................... 20 Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Page Functional Diagram...................................3 28-Pin PLCC.............................................4 Ring Trip Circuits ....................................12 L9219 Basic Test Circuit.........................13 Metallic PSRR.........................................13 Longitudinal PSRR .................................13 Longitudinal Balance ..............................14 RFI Rejection ..........................................14 Longitudinal Impedance..........................14 ac Gains..................................................14 Basic Loop Start Application Circuit Using T7504-Type Codec............15 Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec............17 2 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Description (continued) BGND AGND IPROG CF1 CF2 FB1 VCC FB2 POWER CONDITIONING AND REFERENCE FORWARD AND REVERSE BATTERY RECTIFIER 3 DCOUT VTX = 41 V/A TG TXI AAC PT TIP/RING CURRENT SENSE PR + A = -1 - A VERSION GAIN = 3.93 G VERSION GAIN = 1 - A=1 + = 9.66 VITR + AX - - + RCVN RCVP B0 BATTERY FEED STATE CONTROL B1 B2 LCTH LOOP CLOSURE DETECTOR + - THERMAL SHUTDOWN RTSP RTSN RING TRIP DETECTOR + NSTAT - TSD 12-3557 (F).c Figure 1. Functional Diagram Agere Systems Inc. 3 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Pin Information IPROG TSD FB1 FB2 VCC NC TG 26 25 VTX 24 4 RCVP 5 3 2 1 28 27 RCVN 6 TXI LCTH 7 23 VITR DCOUT 8 28-PIN PLCC 22 NSTAT VBAT 9 21 NC PR 10 20 RTSP CF2 11 12 CF1 13 B2 14 B1 15 B0 16 AGND 17 BGND 18 PT 19 RTSN 12-3558 (F) Figure 2. 28-Pin PLCC Table 1. Pin Descriptions PLCC Symbol Type Description 1 IPROG I Current-Limit Program Input. A resistor to DCOUT sets the dc current limit of the device. The value of current limit set via this resistor may be increased via logic control (see state table for additional detail). 2 FB2 -- Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of battery reversal. 3 FB1 -- Polarity Reversal Slowdown. Connect a capacitor to ground to control the rate of battery reversal. 4 VCC -- 5 V Power Supply. 5 RCVP I Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. 6 RCVN I Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. 4 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Pin Information (continued) Table 1. Pin Descriptions (continued) PLCC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol LCTH DCOUT VBAT PR CF2 CF1 B2 B1 B0 AGND BGND PT RTSN RTSP NC NSTAT VITR TXI VTX TG TSD NC Type Description I Loop Closure Threshold Input. Connect a resistor to DCOUT to set off-hook threshold. O dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. -- Battery Supply. Negative high-voltage power supply. I/O Protected Ring. The output of the ring driver amplifier and input to loop sensing circuitry. Connect to the loop through overvoltage protection. -- Filter Capacitor 2. Connect a 0.1 F capacitor from this pin to AGND. -- Filter Capacitor 1. Connect a 0.47 F capacitor from this pin to pin CF2. I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B2 has internal pull-down. I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B1 has internal pull-down. I State Control Input. B0, B1, and B2 determine the state of the SLIC. See Table 2. Pin B0 has internal pull-down. -- Analog Signal Ground. -- Battery Ground. Ground return for the battery supply. I/O Protected Tip. The output of the tip driver amplifier and input to loop sensing circuitry. Connect to loop through overvoltage protection. I Ring Trip Sense Negative. Connect this pin to the ringing generator signal through a high-value resistor. I Ring Trip Sense Positive. Connect this pin to the ring relay and the ringer series resistor through a high-value resistor. -- No Connect. O Ring Trip Detector Output/Loop Detector Output. When low, this logic output indicates that ringing is tripped or that an off-hook condition exists. O ac Output Voltage. The voltage at this point is directly proportional to the differential tip/ring current. I ac/dc Separation. Connect a 0.1 F capacitor from this point to VTX. O ac and dc Output Voltage. This output is a voltage that is directly proportional to the differential tip/ring current. -- Transmit Gain. Connect an 8.06 k from TG to VTX to set the transmit gain of the SLIC. O Thermal Shutdown. When high, this logic output indicates the device is in thermal shutdown. -- No Connect. Agere Systems Inc. 5 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Functional Description Table 2. Input State Coding B0 1 1 1 B1 1 0 1 B2 State/Definition 1 Powerup, Forward Battery. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. Current limit is set per RPROG resistor. 1 Powerup, Reverse Battery. Normal talk and battery feed state. Pin PT is negative with respect to PR. On-hook transmission is enabled. Current limit is set per RPROG resistor. 0 Powerup, Forward Battery, High Current Limit. Normal talk and battery feed state. Pin PT is positive with respect to PR. On-hook transmission is enabled. Current limit is a nominal 1.4 times higher than setting per RPROG resistor. 0 Powerup, Reverse Battery, High Current Limit. Normal talk and battery feed state. Pin PT is negative with respect to PR. On-hook transmission is enabled. Current limit is a nominal 1.4 times higher than setting per RPROG resistor. 1 Low-Power Scan. Except for off-hook detection, all circuits are shut down to conserve power. Pin PT is positive with respect to pin PR. On-hook transmission is disabled. 1 Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance state (>100 k). Supervision outputs read on hook. Device will power up in this state. 0 Disconnect. The tip and ring amplifiers are turned off, and the SLIC goes to a high-impedance state (>100 k). Supervision outputs read on hook. Device will power up in this state. 0 Low-Power Scan. Except for off-hook suppression, all circuits are shut down to conserve power. Pin PT is positive with respect to pin PR. On-hook transmission is disabled. 1 0 0 0 0 0 1 0 0 1 Table 3. Supervision Coding NSTAT 0 = off-hook or ring trip. 1 = on-hook and no ring trip. TSD 0 = Normal device operation. 1 = Device is in thermal shutdown. 6 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Absolute Maximum Ratings (at TA = 25 C) Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter 5 V Power Supply Battery (Talking) Supply Logic Input Voltage Analog Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) PT or PR Fault Voltage (dc) PT or PR Fault Voltage (10 x 1000 s) Current into Ring Trip Inputs Symbol VCC VBAT -- -- TJ Tstg RH -- VPT, VPR VPT, VPR IRTSP, IRTSN Min -- -- -0.5 -7.0 150 -40 5 -- VBAT - 5 VBAT - 15 -- Typ -- -- -- -- -- -- -- 3 -- -- 240 Max 7.0 -75 7.0 7.0 -- 125 95 -- 3 15 -- Unit V V V V C C % V V V A Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are the following: 1. An inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters. 2. Inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage. Recommended Operating Conditions Parameter Ambient Temperature VCC Supply Voltage VBAT Supply Voltage Min -40 4.75 -24 Typ -- 5.0 -48 Max 85 5.25 -70 Unit C V V Agere Systems Inc. 7 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Electrical Characteristics Minimum and maximum values are testing requirements in the temperature range of 25 C to 85 C and battery range of -24 V to -70 V. These minimum and maximum values are guaranteed to -40 C based on component simulations and design verification of samples, but devices are not tested to -40 C in production. The test circuit shown in Figure 4 is used, unless otherwise noted. Positive currents flow into the device. Typical values are characteristics of the device design at 25 C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are VCC = 5.0 V, VBAT = -48 V, unless otherwise noted. Table 4. Power Supply Parameter Power Supply--Powerup, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply--Scan, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply--Disconnect, No Loop Current: ICC IBAT (VBAT = -48 V) Power Dissipation (VBAT = -48 V) Power Supply Rejection 500 Hz to 3 kHz (See Figure 5 and Figure 6)1: VCC VBAT Thermal Protection Shutdown (Tjc)3 Thermal Resistance, Junction to Ambient (JA)2, 3: Natural Convection 2S2P Board Natural Convection 2S0P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board Min -- -- -- -- -- -- -- -- -- Typ 4.6 -2.4 138 2.8 -0.8 52 1.6 -0.12 14 Max 5.6 -2.7 158 3.8 -1.0 67 -- -- -- Unit mA mA mW mA mA mW mA mA mW 30 40 150 -- -- -- -- -- -- 165 30 43 27 36 -- -- -- -- -- -- -- dB dB C C/W C/W C/W C/W 1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. Careful thermal design as a function of maximum battery, loop length, maximum ambient temperature package thermal resistance, airflow, PCB board layers, and other related parameters must ensure that thermal shutdown temperature is not exceeded under normal use conditions. 3. Airflow, PCB board layers, and other factors can greatly affect this parameter. 8 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Electrical Characteristics (continued) Table 5. 2-Wire Port Parameter Tip or Ring Drive Current = dc + Longitudinal + Signal Currents Signal Current Longitudinal Current Capability per Wire 1 Min 80 15 8.5 15 -- -- |VBAT + 7.5| |VBAT + 8.0| -- -- Typ -- -- 15 -- 5 VBAT/2 |VBAT + 6.5| |VBAT + 6.5| 10 70 Max -- -- -- 45 -- -- |VBAT + 5.9| |VBAT + 5.9| 150 100 Unit mA mArms mArms mA % V V V A dc Loop Current Limit2: Allowed Range Including Tolerance3 Accuracy (RLOOP = 100 , VBAT = -48 V) Powerup Open Loop Voltage Levels: Common-mode Voltage Differential Voltage VBAT = -48 V4 (Gain = 2) Differential Voltage VBAT = -48 V4 (Gain = 7.86) Disconnect State: Leakage dc Feed Resistance (for ILOOP below regulation level) (does not include protection resistor) Loop Resistance Range (-3.17 dBm overload into 900 ; not including protection): ILOOP = 20 mA at VBAT = -48 V Longitudinal to Metallic Balance--IEEE Std. 455 (See Figure 7)5: 200 Hz to 3400 Hz Metallic to Longitudinal Balance (open loop): 200 Hz to 4 kHz RFI Rejection (See Figure 8)3, 0.5 Vrms, 50 Source, 30% AM Mod 1 kHz: 500 kHz to 100 MHz (R) 1800 -- -- 58 40 -- -- 61 -- -- -55 -- -- -- -45 dB dB -- dBV 1. The longitudinal current is independent of dc loop current. 2. Current-limit ILIM is programmed by a resistor, RPROG, from pin IPROG to DCOUT. ILIM is specified at the loop resistance where current limiting begins (see Figure 13). 3. This parameter is not tested in production. It is guaranteed by design and device characterization. 4. Specification is reduced to |VBAT1 + 10.5 V| minimum when VBAT1 = -70 V at 85 C. 5. Longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. More information is available in the Applications section of this document. Agere Systems Inc. 9 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Electrical Characteristics (continued) Table 6. Analog Pin Characteristics Parameter Differential PT/PR Current Sense (DCOUT): Gain (PT/PR to DCOUT) Offset Voltage at ILOOP = 0 Loop Closure Detector Threshold (RLCTH = 22.1 k)1: On-hook to Off-hook Threshold (scan mode) Off-hook to On-hook Threshold (active mode) Ring Trip Comparator: Input Offset Voltage2 Internal Voltage Source Current at Input RTSP3 RCVN, RCVP: Input Bias Current Input Resistance Min 121 -100 8.8 6.0 -- -9.1 IN - 0.5 -- -- Typ 125 -- -- -- 10 -8.6 IN -0.2 1 Max 129 100 13.6 10.2 -- -8.1 IN + 0.6 -1 -- Unit V/A mV mA mA mV V A A M 1. Loop closure threshold is programmed by resistor RLCTH from pin LCTH to pin DCOUT. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. IN is the sourcing current at RTSN. Guaranteed if IN is within 5 A to 30 A. 10 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Electrical Characteristics (continued) Table 7. ac Feed Characteristics Parameter ac Termination Impedance 1 Min 150 -- -- -- -391 7.62 -7.62 1.94 -1.94 Typ -- 0 -- -- -403 7.86 -7.86 2.00 -2.00 Max 1300 -- 0.3 1.0 -415 8.09 -8.09 2.06 -2.06 Unit % % V/A -- -- -- -- Longitudinal Impedance at PT/PR2 Total Harmonic Distortion--200 Hz to 4 kHz2: Off-hook On-hook Transmit Gain, f = 1 kHz (PT/PR to VITR) (current limit) L9219A, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)3 Receive - Gain, f = 1 kHz (RCVN to PT/PR)3 L9219G, Open Loop: Receive + Gain, f = 1 kHz (RCVP to PT/PR)4 Receive - Gain, f = 1 kHz (RCVN to PT/PR)4 Gain vs. Frequency (transmit and receive) (600 termination; reference 1 kHz2): 200 Hz to 300 Hz 300 Hz to 3.4 kHz 3.4 kHz to 16 kHz 16 kHz to 266 kHz Gain vs. Level (transmit and receive)(reference 0 dBV2): -55 dB to +3 dB 2-wire Idle-channel Noise (600 termination): Psophometric2 C-message 3 kHz Flat2 Transmit Idle-channel Noise: Psophometric2 C-message 3 kHz Flat2 -1.00 -0.3 -3.0 -- -0.05 -- -- -- -- -- -- 0.0 0.0 -0.1 -- 0 -87 2 10 -82 7 15 0.05 0.05 0.3 2.5 0.05 -77 12 20 -77 12 20 dB dB dB dB dB dBmp dBrnC dBrn dBmp dBrnC dBrn 1. With a first-generation codec, this parameter is set by external components. Any complex impedance R1 + R2 || C between 150 and 1300 can be synthesized. With a third-generation codec, this parameter is set by a codec or by a combination of a codec and an external network. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. Use this gain option with a first-generation or third-generation codec. 4. Use this gain option with an Agere third-generation codec. Agere Systems Inc. 11 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Electrical Characteristics (continued) Table 8. Logic Inputs and Outputs All outputs are open collectors with internal, 30 k pull-down resistor. Input pins have internal pull-down or some method to power up in the disconnect state. Parameter Input Voltages: Low Level (permissible range) High Level (permissible range) Input Currents: Low Level (VCC = 5.25 V, VI = 0.4 V) High Level (VCC = 5.25 V, VI = 2.4 V) Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 4.75 V, IOL = 200 A) High Level (VCC = 4.75 V, IOH = -20 A) Symbol VIL VIH IIL IIH VOL VOH Min -0.5 2.0 0 +10 0 2.4 Typ 0.4 2.4 +4 +24 0.2 -- Max 0.7 VCC +10 +50 0.4 VCC Unit V V A A V V Ring Trip Requirements 8 F s Ringing signal: -- Voltage, minimum 35 Vrms, maximum 100 Vrms. -- Frequency, 17 Hz to 33 Hz. -- Crest factor, 1.2 to 1.6. Ring trip: -- 100 ms (typical). Pretrip: -- The circuits in Figure 3 will not cause ring trip. TIP 10 k RING s 2 F TIP 100 RING 12-2572 (F).f s Figure 3. Ring Trip Circuits 12 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Test Configurations VBAT 0.1 F VCC 0.1 F VBAT TIP 50 PT BGND VCC AGND VITR XMT 75 k RLOOP 100 /600 L9219A SLIC RING 50 PR DCOUT 43.2 k IPROG 22.1 k LCTH 2 M RTSP 402 274 k 2 M VBAT RTSN RCVN RCVP 46 k RCV 19.4 k 8.06 k TG VTX TXI B0 B1 B2 NSTAT TSD CF1 CF2 0.47 F 0.1 F 12-3559C (F) 0.1 F Figure 4. L9219 Basic Test Circuit VBAT OR VCC 100 4.7 F VS VBAT OR VCC TIP 67.5 TIP 10 F + VM - VS VT/R 12-2582 (F).b VBAT OR VCC 100 4.7 F VS VBAT OR VCC DISCONNECT BYPASS CAPACITOR DISCONNECT BYPASS CAPACITOR + 900 VT/R BASIC TEST CIRCUIT 56.3 BASIC TEST CIRCUIT RING - 67.5 10 F RING PSRR = 20log PSRR = 20log VS VM 12-2583 (F).b Figure 5. Metallic PSRR Figure 6. Longitudinal PSRR Agere Systems Inc. 13 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Test Configurations (continued) ILONG 100 F TIP VS 368 368 TIP + VPT - - VPR + + VM BASIC TEST CIRCUIT RING ILONG BASIC TEST CIRCUIT - 100 F RING LONGITUDINAL BALANCE = 20 log VS VM ZLONG = VPR VPT OR ILONG ILONG 12-2585 (F).a 12-2584 (F).c Figure 7. Longitudinal Balance Figure 9. Longitudinal Impedance 0.01 F 600 50 VS 0.01 F 82.5 TIP 1 6, 7 L7591 4 2 VBAT BASIC TEST CIRCUIT TIP XMT BASIC TEST CIRCUIT + 600 VT/R 2.15 F 82.5 RING - RING RCV VS HP 4935A TIMS 5-6756 (F).b (R) VS = 0.5 Vrms 30% AM 1 kHz modulation, f = 500 kHz--1 MHz device in powerup mode, 600 termination. GXMT = GRCV = VXMT VT/R VT/R VRCV 12-2587 (F).e Figure 8. RFI Rejection Figure 10. ac Gains 14 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Applications A basic loop start reference circuit, using bused ringing with the L9219 SLIC and the T7504 first-generation codec, is shown in Figure 11. This circuit is designed for a 200 + 680 || 0.1 F complex termination impedance and transhybrid. Transmit gain is set at 0 dBm and receive gain is set at -7 dBm. VBAT CBAT 0.1 F RPROG 35.7 k RLCTH 22.1 k 8 DCOUT TXI VITR TIP RPT 50 EMR LCAS RING RPR 50 RTSP 2.94 M RTS1 402 CRTS1 0.015 F RTSN 3.32 M VRING L7591 18 PT 24 23 7 1 IPROG LCTH VTX 9 VBAT VCC CCC 0.1 F 4 VCC 26 25 RGS 2.37 k RGP1 8.06 k CB 0.1 F RT2 80.6 k RX 158 k CB1 0.47 F - RHB1 357 k RRCV 137 k RGP 30.1 k 6 27 22 13 14 15 CGN 0.1 nF RN1 143 k CB2 0.47 F VFRO + DX +2.4 V DR FSX FSR MCLK CONTROL AND CLOCK PCM HIGHWAY GSX CGS 6.8 nF TG RT1 71.5 k L9219 SLIC 10 PR RCVP 5 RCVN 20 TSD RTSP NSTAT B2 B1 B0 RN2 18.2 k SUPERVISION OUTPUTS 1/4 T7504 CODEC CONTROL INPUTS 19 RTSN CF2 11 CF1 12 CF1 0.47 F CF2 0.1 F AGND BGND 17 16 VBAT 12-3560 (F).g Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec Table 9 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted to program these values are also shown. Table 9. 200 + 680 || 0.1 F First-Generation Codec Design Parameters Design Parameter Loop Closure Threshold dc Loop Current Limit 2-wire Signal Overload Level ac Termination Impedance Hybrid Balance Line Impedance Transmit Gain Receive Gain Parameter Value 10 mA 25 mA 3.14 dBm 200 + 680 || 0.1 F 200 + 680 || 0.1 F 0 dBm -7 dBm Components Adjusted RLCTH RPROG -- RT1, RGP, RRCV, RGP1, RGS, CGS RHB1 RT2, RX, RN1, RN2, CN RRCV, RGP, RT1 Agere Systems Inc. 15 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Applications (continued) Table 10. Parts List for Loop Start Application Circuit Using T7504-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Characteristics RPROG ac Characteristics CB1 CB2 CB RT1 RRCV RGP RT2 RX RHB1 CGS RGS RGP1 CN RN1 RN2 Supervision RLCTH RTS1 CRTS1 RTSN RTSP Value L9219 Agere L7591 Agere L7581/2/3 or EMR T7504 50 , Fusible 50 , Fusible 0.1 F, 20%, 100 V 0.1 F, 20%, 10 V 0.47 F, 20%, 100 V 0.1 F, 20%, 100 V 35.7 k, 1%, 1/16 W 0.47 F, 20%, 10 V 0.47 F, 20%, 10 V 0.1 F, 20%, 10 V 71.5 k, 1%, 1/16 W 137 k, 1%, 1/16 W 30.1 k, 1%, 1/16 W 80.6 k, 1%, 1/16 W 158 k, 1%, 1/16 W 357 k, 1%, 1/16 W 6.8 nF, 10%, 10 V 2.37 k, 1%, 1/16 W 8.06 k, 1%, 1/16 W 0.1 nF, 20%, 10 V 143 k, 1%, 1/16 W 18.2 k, 1%, 1/16 W 22.1 k, 1%, 1/16 W 402 , 5%, 2 W 0.015 F, 20%, 10 V 3.32 M, 1%, 1/16 W 2.94 M, 1%, 1/16 W Function Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. First-generation codec. Protection resistor. Protection resistor. VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. Set low current limit. ac/dc separation capacitor. ac/dc separation capacitor. dc blocking capacitor. With RGP and RRCV, sets ac termination impedance. With RGP and RT1, sets receive gain. With RT1 and RRCV, sets ac termination impedance and receive gain. With RX, sets transmit gain in codec. With RT2, sets transmit gain in codec. Sets hybrid balance. With RGS, provides gain shaping for termination impedance matching. With CGS, provides gain shaping for termination impedance matching. Sets dc transmit gain of SLIC. With RN1 and RN2 high frequency compensation. With CN and RN2 high frequency compensation. With RN1 and CN high frequency compensation. Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN, RTSP, forms filter pole. With RTSP, sets threshold. With CRTS1, RTSN, sets threshold. 16 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Applications (continued) A basic loop start reference circuit, using bused ringing with the L9219 SLIC and the T8536 third-generation codec, is shown in Figure 12. VBAT CBAT 0.1 F RPROG 35.7 k RLCTH 22.1 k 8 7 1 IPROG LCTH DCOUT 9 VBAT 4 VCC TG VTX 26 25 RGP1 8.06 k CB 0.1 F CB1 0.1 F RCIN 20 M VCC CCC 0.1 F TXI TIP RPT 50 EMR LCAS RING RPR 50 RTSP 2.94 M RTS1 510 CRTS1 0.015 F RTSN 3.4 M VRING L7591 10 PR 20 18 PT 24 VITR 23 5 6 22 15 14 13 VFXI 1/4 T8536 CODEC DX2 DR1 DR2 FS BCLK VDD DX1 PCM HIGHWAY L9219 SLIC RCVP RCVN NSTAT B0 VFROP VFRON SLIC0a SLIC3a SLIC2a SLIC4a CONTROL AND CLOCK RTSP B1 B2 CVDD 0.1 F DGND 19 RTSN CF2 11 CF1 12 CF1 0.47 F CF2 0.1 F 12-3561 (F).d AGND BGND 16 17 VBAT Figure 12. Basic Loop Start Application Circuit Using T8536-Type Codec Agere Systems Inc. 17 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Applications (continued) Table 11. Parts List for Loop Start Application Circuit Using T8536-Type Codec Name Integrated Circuits SLIC Protector Ringing Relay Codec Overvoltage Protection RPT RPR Power Supply CBAT1 CCC CF1 CF2 dc Characteristics RPROG ac Characteristics CB1 CB RGP1 RCIN Supervision RLCTH RTS1 CRTS1 RTSN RTSP Value L9219 Agere L7591 Agere L7581/2/3 or EMR T8536 50 , Fusible 50 , Fusible 0.1 F, 20%, 100 V 0.1 F, 20%, 10 V 0.47 F, 20%, 100 V 0.1 F, 20%, 100 V 35.7 k, 1%, 1/16 W 0.1 F, 20%, 10 V 0.1 F, 20%, 10 V 8.06 k, 1%, 1/16 W 20 M, 5%, 1/16 W 22.1 k, 1%, 1/16 W 510 , 5%, 2 W 0.015 F, 20%, 10 V 3.4 M, 1%, 1/16 W 2.94 M, 1%, 1/16 W Function Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals. Third-generation codec. Protection resistor. Protection resistor. VBAT filter capacitor. VCC filter capacitor. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. Set low current limit. ac/dc separation capacitor. dc blocking capacitor. Sets dc transmit gain of SLIC. dc bias. Sets loop closure (off-hook) threshold. Ringing source series resistor. With RTSN and RTSP, forms second 2 Hz filter pole. With RTSP, sets threshold. With RTSN, sets threshold. 18 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Starting from the on-hook condition and going through to a short circuit, the curve passes through the following two regions: Region 1: On-hook and low loop currents. The slope corresponds to the dc resistance of the SLIC, Rdc1 (default is 70 typical). The open circuit voltage is the battery voltage minus the overhead voltage of the device, VOH (default is 6.5 V typical). These values are suitable for most applications, but can be adjusted if needed. For more information, see the sections entitled Adjusting dc Feed Resistance and Adjusting Overhead Voltage. Region 2: Current limit. The dc current is limited to a starting value determined by external resistor RPROG, the logic table, an internal current source, and the gain from tip/ring to pin VITR. Current Limit With the logic inputs set to 11 (a low current limit active state), current limit with a 100 load is given by the following: 0.637 RPROG (k) + 2 mA = ILIM x (mA) Applications (continued) dc Applications Battery Feed The dc feed characteristic can be described by: VT/R = ( VBAT - VOH ) x R L -------------------------------------------RL + 2RP + Rdc IL = RL + 2RP + Rdc VBAT - VOH --------------------------------- where: IL = dc loop current. VT/R = dc loop voltage. |VBAT| = battery voltage magnitude. VOH = overhead voltage. This is the difference between the battery voltage and the open loop tip/ring voltage. RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. 50 LOOP CURRENT (mA) 40 ILIM TESTED 1 12.5 k ILIM ONSET Via the logic table, the current limit can be increased a nominal 42% from the value set by the RPROG resistor. The relationship between low current limit and high current limit is as follows: ILIMIT ( Low ) ---------------------------------- = 0.7 ILIMIT ( High ) 30 20 -1 Rdc1 Overhead Voltage In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the battery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage and is expressed as the following equation: VOH = |VBAT| - (VPT - VPR) Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. The L9219 is automatically set at the factory to allow undistorted on-hook transmission of a 3.14 dBm signal into a 900 loop impedance. 10 0 0 10 30 20 LOOP VOLTAGE (V) 40 50 12-3050 (F).i Notes: VBAT = -48 V. ILIM = 22 mA. Rdc1 = 80 . Figure 13. Loop Current vs. Loop Voltage Agere Systems Inc. 19 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Off-Hook Detection The loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 Hz filter. The loop closure detection threshold is set by resistor RLCTH. The supervision output bit (NSTAT) is high in an on-hook condition. The off-hook comparator goes low during an off-hook condition: ITR (mA) = 0.4167 RLCTH (k) - 1.9 mA ACTIVE off-hook to on-hook ITR (mA) = 0.4167 RLCTH (k) + 2.7 mA SCAN on-hook to off-hook RP ITR RL RING RP 0.05 mA LCTH + - NSTAT TIP + - RLCTH 0.125 V/mA DCOUT Applications (continued) dc Applications (continued) Rate of Battery Reversal The rate of battery reversal is controlled or ramped by capacitors FB1 and FB2. A chart showing FB1/FB2 values versus typical ramp rate is given below. Leave FB1/FB2 open if it is not desired to ramp the rate of battery reversal. Table 12. FB1/FB2 Values vs. Typical Ramp Time CFB1/CFB2 0.01 F 0.1 F 0.22 F 0.47 F 1.0 F 1.22 F 1.3 F 1.4 F 1.6 F Loop Range The equation below can be rearranged to provide the loop range for a required loop current: RL = VBAT - VOH --------------------------- - 2RP - RDC IL Transition Time 20 ms 220 ms 440 ms 900 ms 1.8 s 2.25 s 2.5 s 2.7 s 3.2 s 12-2553 (F).f Figure 14. Off-Hook Detection Circuit 20 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Applications (continued) dc Applications (continued) Ring Trip Detection The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent circuit is shown in Figure 15, along with its use in an application using unbalanced, battery-backed ringing. PHONE HOOK SWITCH RLOOP RC PHONE RTSP 2.94 M RS 402 /510 RTSN 3.32 M/3.40 M RTSN CRTS1 0.015 F - 15 k IP = IN IN + - 8.6 V RTSP + NSTAT VBAT VRING 2799 (F) Figure 15. Ring Trip Equivalent Circuit and Equivalent Application Ring trip detection threshold is given by the following equation: [ RTSN ( M ) + 0.015 - RTSP ( M ) ] x [ VBAT - 8.6 ] x 1000 ITH (mA) = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------[ RTSN ( M ) + 0.015 ] x RS Longitudinal Balance The SLIC is graded to certain longitudinal balance specifications. The numbers are guaranteed by testing (Figure 5 and Figure 8). However, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. This can be illustrated by the following equation: ( 368 + RP ) x ( 368 + ZT - RP ) LB = 20 x log ------------------------------------------------------------------------------------------368 x ( 2 x [ ZT - 2 x RP ] x + ) where: LB: longitudinal balance RP: protection resistor value in ZT: magnitude of the termination impedance in : protection resistor mismatch in : SLIC internal tip/ring sensing mismatch The can be calculated using the above equation with these exceptions: = 0, ZT = 600 , RP = 100 , and the longitudinal balance specification on a specific code. Now with available, the equation will predict the actual longitudinal balance for RP, ZT, and . Be aware that ZT may vary with frequency for complex impedance applications. Agere Systems Inc. 21 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 ac Interface Network The ac interface network between the L9219 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9219 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9219 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal-to-noise ratio (S/N) in the receive direction. Receive Interface Because the design requirements are very different with a first- or third-generation codec, the L9219 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9219 and codec. With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9219 provides a transconductance from T/R to VITR in the transmit direction and a single ended to differential gain in the receive direction from either RCVN or RCVP to T/R. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance times the SLIC receive gain, plus the protection resistors. The various specified termination impedance can range over the voice band as low as 300 up to over 1000 . Thus, if the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Furthermore, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason a high-gain SLIC is required with a first-generation codec. Applications (continued) ac Design Codec Types At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. Below is a brief codec feature summary. First-Generation Codecs. These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, 5 V only or 5 V operation, and -law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Furthermore, ac parameters are fixed by the external R/C network, so software control of ac parameters is difficult. Third-Generation Codecs. This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, TTX generation, test algorithms, and echo cancellation. Again, this type of codec may be 5 V only or 5 V operation, single quad or 16-channel, and -law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and the T8531/36 (5 V only 16-channel with self-test). 22 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit high-gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operating near maximum signal levels, thus compromising the S/N. It appears the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency to meet the return loss requirements. Further stability issues may add external components or excessive ground plane requirements to the design. To meet the unique requirements of both types of codecs, the L9219 offers two receive gain choices. These receive gains are mask-programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9219A is offered with a receive gain of 7.86. For interface with a third-generation codec, the L9219G is offered with a receive gain of 2. In either case, the transconductance in the transmit direction, or the transmit gain, is 403 . Applications (continued) ac Design (continued) Receive Interface (continued) With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and transmission level points (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voice band frequency, must ensure that the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input. In the receive direction, the issue is to optimize S/N. Again, the designer must consider all the considered TLPs. The idea is, for all desired TLPs, to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember noise floor is constant, so the hotter the signal from the codec, the better the S/N. The problem is, if the codec is feeding a Example 1: Real Termination (First-Generation Codec) ac equivalent circuits for real termination using a T7504 codec is shown in Figure 23. RX VGSX -0.403 V/mA VITR RCVN RCVP RG + AV = -1 - L9219 SLIC RT2 VFXIN - VFXIP + 2.4 V VFR RT1 RHB1 RRCV ZT/R RP TIP VS IT/R + ZT VT/R - RP RING - AV = 1 + CURRENT SENSE - AV = 3.93 + 1/4 T7504 CODEC 12-3581 (F).c Figure 16. ac Equivalent Circuit Agere Systems Inc. 23 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Applications (continued) ac Design (continued) Example 1: Real Termination (First-Generation Codec) (continued) The following design equations refer to the circuit in Figure 16. Use these to synthesize real termination impedance. Termination Impedance: VT R ZT = -------------- IT R 3168 ZT = 2RP + ---------------------------------RT3 RT3 1 + -------- + ----------RGP RRCV Receive Gain: VT R grcv = ------------Vfr 7.86 grcv = -----------------------------------------------------------------------------------RRCV RRCV ZT 1 + -------------- + -------------- 1 + ------------ RT3 RGP ZT/R Transmit Gain: VGSX gtx = -------------VT R RX 403 gtx = ---------- x ---------ZT RT6 Hybrid Balance: VGSX hbal = 20log -------------VT R To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The following expressions assume the test network is the same as the termination impedance: RX RHB = -----------------------gtx x grcv RXhbal = 20log ----------- - gtx x grcv RHB 24 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) Below are design equations for complex termination (see Figure 17 and Figure 18). ZT = RT1 + RT2 || CT 7.86 RT1 = 2RP + ----------201.2 1 1 ---------------------------------- - ----------------- * RT3 RN1 1 + -------- + ----------- 1 + ------- - RT3 RGP RRCV RN2 RTGP || RTGS RT2 = 7.86 RTGP RTGS 1 ----------- * ---------------------------------- + ----------------- RTGP || RTGS - 201.2 RN1 RT3 - RT31 + -------- + ----------- 1 + ------- RGP RRCV RN2 7.86- 1 RN2 1RTGP - 2 1 1 = --------------- ---------- ------------------------------------ RTGP || RTGS + ---------- * ------------------------------------ * --------------------------------------------- - --------------------- CTG RTGP + RTGS CT 201.2 CN1 ( RN1 + RN2 ) 2 RT3 RN1 RT3 1 + ----------- + -------------- 1 + ---------- RGP RRCV RN2 1-----RX 1 ZTG gtx = ---------- ---------------- ---------RT6 201.2 ZT 7.86 1grcv = ----------------------------------------------- x ----------------------RRCV RRCV ZT 1 + --------------- + --------------- 1 + ------------RT3 RGP ZT R RXhbal = 20log ----------- - gtx x grcv RHB where: ZT/R = R1 + R2 || C ZTG = RTGP || (RTGS + CG) RTGP = 8.06 k R1 RTGS = ------- RTGP R2 R2 2 CG = ----------------------------------------- x C RTGP ( R1 + R2 ) and 2RP CNRN2 = ------------ CG RTGP 3038 3038 RTGS RN1 = RN2 ------------ ------------- - 1 2RP RTGP The equations above do not include the blocking capacitors. Agere Systems Inc. 25 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Applications (continued) ac Design (continued) Example 2: Complex Termination (First-Generation Codec) (continued) RTGS CGS RX -IT/R 201.2 RTGP = 8.06 k CB AX AAC RT6 - + CODEC OP AMP CN RN1 RCVN RCVN RCVP RCVP RN2 RRCV RGP RT3 CODEC OUTPUT DRIVE AMP 5-6401 (F).j Figure 17. Interface Circuit Using First-Generation Codec (5 V Battery) RTGS CG RX -IT/R 201.2 RTGP = 8.06 k RT6 AX CB AAC CB1 - + CODEC OP AMP -2.4 V CN RN1 RCVN RCVP RGP RN2 RT3 RRCV CB2 CODEC OUTPUT DRIVE AMP 5-6400 (F).n Figure 18. Interface Circuit Using First-Generation Codec (5 V Only Codec) 26 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Loop power = (25 mA * 1.05)2 * (200 + 100 ) Loop power = 0.207 W SLIC power = 1.523 W - 0.207 W = 1.28 SLIC power = 1.28 W < 1.51 W Thus, in this example, the thermal design ensures that the SLIC will not enter the thermal shutdown state. Applications (continued) Power Derating Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and protection resistor values will influence the overall thermal performance. This section shows the relevant design equations and considerations in evaluating the SLIC thermal performance. Consider the L9219 SLIC in a 28-pin PLCC package. The still-air thermal resistance on a 2 layer board is 43 C/W. The SLIC will enter the thermal shutdown state at minimally 150 C. The thermal shutdown design should ensure that the SLIC temperature does not reach 150 C under normal operating conditions. Assume a maximum ambient operating temperature of 85 C, a maximum current limit of 25 mA (including tolerance), and a maximum battery of -52 V. Furthermore, assume a (worst case) minimum dc loop of 200 , and that 50 protection resistors are used at both tip and ring. 1. TTSD - TAMBIENT(max) = allowed thermal rise. 150 C - 85 C = 65 C 2. Allowed thermal rise = package thermal impedance * SLIC power dissipation. 65 C = 43 C/W * SLIC power dissipation SLIC power dissipation (PDISS) = 1.51 W Thus, if the total power dissipated in the SLIC is less than 1.51 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total PDISS = Maximum battery * Maximum current limit (including effects of accuracy) + SLIC quiescent power. For the L9219, SLIC quiescent power (PQ) is maximum at 0.158 W. Thus, Total PDISS = (-52 V * [25 mA * 1.05]) + 0.158 W Total PDISS = 1.365 W + 0.158 W Total PDISS = 1.523 W The power dissipated in the SLIC is the total power dissipation minus the power that is dissipated in the loop. SLIC PDISS = Total power - Loop power Loop power = (ILIM)2 * (RdcLOOP min + 2RP) Pin-for-Pin Compatibility with L9217/L9218 The L9219 is an exact pin-for-pin replacement for the L9217/18. The one minor exception is L9219 has three logic control inputs: B0, B1, and B2. The L9218 has only two logic control inputs, B0 and B1. Pin 13 in L9218 is NC, so a connection between the controller and pin 13 will not affect L9218 operation. This allows an exact footprint match with L9219. PCB Layout Information Make the leads to BGND and VBAT as wide as possible for thermal and electrical reasons. Also, maximize the amount of PCB copper in the area of (and specifically on) the leads connected to this device for the lowest operating temperature. When powering the device, ensure that no external potential creates a voltage on any pin of the device that exceeds the device ratings. In this application, some of the conditions that cause such potentials during powerup are the following: 1. An inductor connected to PT and PR (this can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters). 2. Inductance in the VBAT lead (this could resonate with the VBAT filter capacitor to cause a destructive overvoltage). This device is normally used on a circuit card that is subjected to hot plug-in, meaning the card is plugged into a biased backplane connector. In order to prevent damage to the IC, all ground connections must be applied before, and removed after, all other connections. Agere Systems Inc. 27 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Data Sheet November 2001 Outline Diagram 28-Pin PLCC Dimensions are in millimeters. 12.446 0.127 11.506 0.076 PIN #1 IDENTIFIER ZONE 4 1 26 5 25 11.506 0.076 12.446 0.127 11 19 12 18 4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.330/0.533 5-2506 (F)r.8 0.10 28 Agere Systems Inc. Data Sheet November 2001 L9219A/G Low-Cost Line Interface with Reverse Battery and Dual Current Limit Ordering Information Device LUCL9219AAR-D Package 28-Pin PLCC (Dry Bag) Gain of 12 28-Pin PLCC (Tape and Reel, Dry Bag) Gain of 12 28-Pin PLCC (Dry Bag) Gain of 2 28-Pin PLCC (Tape and Reel, Dry Bag) Gain of 2 Comcode 108558867 LUCL9219AAR-DT 108558875 LUCL9219GAR-D 108558800 LUCL9219GAR-DT 108558818 Agere Systems Inc. 29 IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. HP is a registered trademark of Hewlett-Packard Company. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved November 2001 DS02-040ALC (Replaces DS01-033ALC) |
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